Tiber communicates with the host via two Flexbus(TM)-3/SPI-3 interfaces, each with three transmit FIFOs (Control, High, Low) and one receive FIFO.
What does TFSBPIS stand for?
TFSBPIS stands for Transmit FIFO (First In, First Out) Starting Block Pointer Indirect Select
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- Information technology (IT) and computers
- Time-Frequency Signal Analysis
- Toronto Financial Services Alliance (Ontario, Canada)
- Total Financial Solutions Australia
- Tank Farm Surveillance, Analysis, And Support
- Time-Frequency Signal Analysis and Processing (book)
- Tennessee Folklore Society Bulletin
- The Fabulous Shaker Boys (Netherlands)
- The Fire Still Burns (band)
- Toyota Financial Savings Bank
- Transmit FIFO (First In, First Out) Starting Block Pointer
- Tanstia-FNF (Friedich Naumann Stiftung) Service Centre (India and Germany)
- Team Foundation Source Control (Microsoft)
- Texas Forensic Science Commission
- Texas Funeral Service Commission
- Theater Finance Support Center
- Theatre Functional Steering Committee
- Thin-Film Solar Cell
- Toshiba Fuchu Soccer Club (Japan)
- Toyota Financial Services Corporation
- Trust Fund for Statistical Capacity Building
Samples in periodicals archive:
The on-chip transmit FIFO allows for a flexible data clocking rate.
Large receive and transmit FIFO buffers eliminate the need for off-chip memory, and on-chip direct memory access (DMA) minimizes CPU intervention.
The XMAC II also integrates 8KB Receive and 4KB Transmit FIFO buffers with programmable thresholds and integral Pause-Frame flow control to minimize system overflows and underruns.
Internal buffer management includes unlimited (limited only by the FIFO size) receive/transmit frame queueing in the FIFO to handle long PCI bus latencies, hardware support for handling transmit collisions and FIFO underruns with no software intervention, and programmable hardware to control transmit FIFO thresholds and to prevent underrun of transmit FIFO and enhance overall system performance.
The single chip communications device saves board space by supporting 4 full-duplex asynchronous channels, each with its own 16-byte receive and 16-byte transmit FIFO.
CDB transmit functions include ATM cell header error correction (HEC) calculation and insertion, automatic generation of idle cells with user-assigned value when the transmit FIFO underruns and optional scrambling of the cells prior to transmission.
Large-capacity FIFO Isochronous FIFO 720 words x 32 bits Asynchronous Transmit FIFO 36 words x 33 bits Asynchronous Receive FIFO 30 words x 33 bits 4.