Other topics include maximizing chip multiprocessor throughput with smaller cores, protein motif finding on a network processor, a trace cache sampling filter, and memory state compressors for giga-scale checkpoint/restore.
What does TC stand for?
TC stands for Trace Cache
This definition appears frequently and is found in the following Acronym Finder categories:
- Information technology (IT) and computers
See other definitions of TC
We have 135 other meanings of TC in our Acronym Attic
- Total Credit (distributive computing; tax calculations)
- TouchChip (biometric sensor)
- Tougaloo College (Jackson, MS)
- Touring Convertible (Chrysler/Maserati)
- Town and Country
- Town Centre (Age of Empires II game)
- Toxic Chemical (hazardous chemicals)
- Toxic Concentration (TC50 = 50% of the population or TClo = low)
- Toxicity Characteristic
- Trabuco Canyon (California)
Samples in periodicals archive:
A new technology called Execution Trace Cache offers a wrinkle in standard Level 1 cache design.
However, the biggest change that AMD has made to the chip is to include serial interface into the chip and 256k trace cache that allows developers to access trace route and register information.
High performance is provided by the Intel(R) NetBurst(TM) Micro-Architecture, consisting of: a 400 MHz processor system bus, Hyper Pipelined Technology, an Execution Trace Cache, Rapid Execution Engine, and 144 Streaming SIMD instructions (SSE2).
Iwill DX400-SN is designed around the Intel(R) Xeon(TM) processors with the Intel(R) NetBurst(TM) micro-architecture which includes several new performance enhancing features such as Hyper Pipelined Technology for higher clock speeds, Streaming SIMD Extensions 2 (SSE2) for improved video, encoding and internet applications, Execution Trace Cache and Rapid Execution Engine for executing instructions at twice the core frequency and 400MHz Intel(R) NetBurst(TM) System Bus.
Execution Trace Cache -- This is an advanced Level 1 instruction cache that caches decoded instructions (~12K micro-ops), thus removing the decoder latency from main execution loop.