Whereas the stuck-at fault model assumes that a cell input or output is always tied to a fixed value, this bridging fault model assumes that one gate will dominate the value driven on the other net via the electrical path through the resistive short ([R.
What does SAF stand for?
SAF stands for Stuck-At Fault
This definition appears somewhat frequently and is found in the following Acronym Finder categories:
- Information technology (IT) and computers
- Science, medicine, engineering, etc.
See other definitions of SAF
We have 317 other meanings of SAF in our Acronym Attic
- Standard Analytical File (Medicare)
- State Aviation Fund (various locations)
- Status - Alpha File
- Stavanger Arkitektforening (Norwegian: Stavanger Architectural Association)
- Store And Forward (JMS message; BEA)
- StoryTellers of the American Frontier
- Strategic Air Force (US DoD)
- Strategic Architect Forum
- Stress Amplification Factor
- Structural Adjustment Facility
- Student Assistance Fund (various locations)
- Students for Academic Freedom
- Study Abroad Fellowship (various universities)
- Study Abroad Foundation
- Subject to Availability of Funds
- Submerged Aeration Filter (waste water treatment)
- Submerged Arc Furnace
- Subnetwork Access Facility
- Summer Arts Festival (various locations)
- Superannuation Funds
Samples in periodicals archive:
With smaller geometries, there are un-modeled (un-anticipated) failure mechanisms that are often missed with the traditional stuck-at fault models used by traditional ATPG tools.
Improving stuck-at fault coverage can typically be improved through standard DFT design techniques such as adding scan wrappers or adding simple test mode controls.
Testing for stuck-at faults and Iddq is adequate to ensure acceptable quality levels for ASICs designed for geometries larger than 130 nm.
This is in addition to our existing 99 percent stuck-at fault coverage capability.
The NEBULA enables remote testing of prototype silicon for stuck-at faults, path-delay faults, at-speed BIST and in-situ functional debug.
A design of this size and complexity requires not only extremely high stuck-at fault coverage, but also thorough testing for delay-related defects, the preponderant defect type in 0.
During extraction of the MAX 3000A programming file, Clear Logic's NoFault(R) tool automatically generates test vectors, derived from the customer's programming file that provide 100% stuck-at fault coverage of the device in the customer's configuration.