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What does SEU stand for?

SEU stands for Single Event Upset (of electronic circuit in space by a heavy particle; proton, etc)

This definition appears very rarely and is found in the following Acronym Finder categories:

  • Science, medicine, engineering, etc.

See other meanings of SEU

Other Resources:
We have 54 other definitions for SEU in our Acronym Attic

Samples in periodicals archive:

April 5, 2013 /PRNewswire/ -- Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced it will host a single event upset (SEU) webinar titled "SEU Immunity: Is Your Design Really Safe?
It describes the foundational issues of the subject, as well as issues that are important for measuring single event upset phenomenon and the interpretation of measurements.
Additional features include: * Up to 540 kbits of embedded memory with optional EDAC protection * Total dose: 300 kRads (functional) and 200 kRads (parametric) * Single event upset (SEU) immunity * Multiple packing options (CQFP and CCGA/LGA) * Screening: E-Flow (Microsemi Extended Flow), B-Flow (Mil-STD-883B), and V-Flow (MIL-PRF-38535 QML Class V) Upcoming Microsemi Space Forums Microsemi's invitation-only, one-day Space Forums address key industry challenges and include technical presentations, new product updates, technology roadmap information and statistical reliability data.
Footnotes DFF: Data Flip Flop LVDS: Low Voltage Differential Swing MCGA: Multi-layer solder Column Grid Array PCI: Peripheral Component Interconnect QFP: Quad Flat Pack SEU: Single Event Upset About Atmel Atmel is a worldwide leader in the design and manufacture of microcontrollers, advanced logic, mixed-signal, nonvolatile memory and radio frequency (RF) components.
27, 2011 /PRNewswire/ -- Highlights: - New Synplify tool capabilities improve error recovery and resistance to single event upsets (SEUs), increasing reliability of FPGAs deployed in the field - Enhanced graphical interface eases status monitoring and debugging in hierarchical design flows - Extended compatibility with Synopsys' Design Compiler tool and DesignWare IP for a robust ASIC prototyping solution Synopsys, Inc.