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What does STI stand for?

Shallow Trench Isolation


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Samples in periodicals archive:
Novellus Systems (Nasdaq: NVLS) today announced that it has developed a manufacturing process to extend the company's SPEED Max shallow trench isolation (STI) application to the 32 nm technology node.
Toshiba is carrying the same principles forward across its flash products, using the shallow trench isolation techniques from the 256Mb DRAM to create the industry's first NAND with shallow trench isolation in its 0.
The LiteEtch TSE was jointly developed by Mattson Technology and a key Japanese customer and is targeted primarily for selective removal of nitride over oxide after shallow trench isolation (STI).
Applied's APF films are already being used in up to seven layers in 70nm Flash memory chips, including shallow trench isolation and sub-40nm gate definition, plus other key applications.
Process control requirements for shallow trench isolation (STI) layers and deep-trench capacitors benefit from ODP's ability to measure complex and high-aspect ratio shapes.
This system has the ability to take repeatable, in-line measurements of shallow trench isolation (STI) and gate structures, as well as contacts and vias in high aspect ratio depth metrology without damaging the device or sacrificing a wafer for cross-sectioned measurements.
ST 100 E[acute accent]ST 100 is an inorganic spin-on oxide for advanced FEOL applications such as Shallow Trench Isolation (STI) and Pre Metal Dielectric (PMD).
The advanced Applied Centura(R) Ultima HDP-CVD(R) is already system of record at both 65nm logic and 70nm memory customers for applications as diverse as shallow trench isolation (STI), pre-metal dielectric (PMD), inter-metal dielectric (IMD) and passivation fill.

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