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- Information technology (IT) and computers
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These devices are based on a new industry architecture that combines high-speed queuing logic with an embedded FIFO memory core to deliver an off-the-shelf building block used to boost performance in hardware implementations of packet scheduling and queuing engines in routers and switches.
The nPX5700 solution consists of the nPX5710 control logic chip (responsible for admission control, scheduling and queuing functions), packaged in a 601-pin PBGA, and the nPX5720 buffering chip (responsible for the management of payload memory), packaged in a 1125-pin PBGA.
0's scheduling and queuing capabilities, users will get better file transfer performance and be more productive.