Deliverables include: register transfer level (RTL) and synthesis scripts, silicon-independent DDR PHY, verification testbench, static timing analysis (STA) scripts, programmable register settings and documentation.
What does RTL stand for?
RTL stands for Register Transfer Level (VHDL)
This definition appears very frequently and is found in the following Acronym Finder categories:
- Information technology (IT) and computers
See other definitions of RTL
We have 100 other meanings of RTL in our Acronym Attic
- Recovery Technical Limit
- Reduced Tillage Linkages
- Redwood Toxicology Laboratory (drug testing facility; Santa Rosa, CA)
- Refrigerated Transmission Line
- Regeneration Thermo-Luminescence
- Regimental Training Line
- Regional Team Leader
- Register Transfer Language
- Register Transfer Level
Samples in periodicals archive:
It works with register transfer level (RTL) and gate-level verification environments, allowing designers to effortlessly accelerate their existing verification environment over pure simulation by 10X to 100X.
ESE offers a unified environment for modeling, software prototyping and implementation, and raises the level of design abstraction above the register transfer level (RTL) for general-purpose ESL implementation.
The Mentor Graphics(R) technology allows the concise specification of a design's low power architectural intent separate from the Register Transfer Level (RTL) HDL code.
It enables high-level hardware synthesis with Quality of Results (QoR) that can match hand-coded Register Transfer Level (RTL), accelerating the time to a verified netlist and reducing verification efforts.
Products include SystemVerilog, VHDL and Verilog parsers, analyzers, and elaborators, as well as a register transfer level (RTL) database.
Calypto will host a daily technical session entitled, "Sequential Equivalence Checking -- A Comprehensive Methodology from System Level Algorithms to Register Transfer Level (RTL) Implementation.
The Novas Siloti SilVE(TM) product optimizes the visibility of the signal data by determining the essential set of probe points required, and then expands and correlates the data to provide full visibility of all internal signals at the register transfer level (RTL) for debug.