The XDR memory architecture features key enabling technologies built on patented Rambus innovations that include low-voltage, low-power Differential Rambus Signaling Level (DRSL); Octal Data Rate (ODR) technology that transfers eight bits of data each clock cycle; FlexPhase[TM] circuit technology for precise on-chip alignment of data with clock; and Dynamic-Point-to-Point (DPP) for both enhanced signal integrity and scalability.
The award-winning XDR memory architecture features key enabling technologies built on patented Rambus innovations that include low-voltage, low-power Differential Rambus Signaling Level (DRSL); Octal Data Rate (ODR) technology that transfers eight bits of data each clock cycle; FlexPhase[TM] circuit technology for precise on-chip alignment of data with clock; and Dynamic-Point-to-Point (DPP) for both enhanced signal integrity and scalability.
The XDR memory architecture uses patented Rambus innovations such as Octal Data Rate (ODR) technology, Differential Rambus Signaling Level (DRSL), and FlexPhase[TM] circuits to deliver the highest bandwidth available while using fewer DRAM devices than industry-standard memory solutions.
The XDR memory architecture features key enabling technologies built on patented Rambus innovations that include low-voltage, low-power Differential Rambus Signaling Level (DRSL); Octal Data Rate (ODR) technology that transfers eight bits of data each clock cycle; FlexPhase[TM] circuit technology for precise on-chip alignment of data with clock; and Dynamic-Point-to-Point (DPP) for both enhanced signal integrity and scalability.
The XIO provides a wide, on-chip, CMOS-level signaling interface to the memory controller logic and a narrow, high-speed Differential Rambus Signaling Level (DRSL) interface to the external XDR memory system.
The XIO provides a wide, on-chip, CMOS-level signaling interface to the memory controller logic and a narrow, high-speed Differential Rambus Signaling Level (DRSL) interface to the external XDR memory system.
Three of the key innovations include: -- Differential Rambus Signaling Level (DRSL) -- a bi-directional differential signaling technology offering a high-performance, low-power, and cost-effective solution for getting bandwidth on and off chip; -- Octal Data Rate (ODR) -- a technology that enables eight bits of data to be transferred on each clock edge, four times as many as today's state-of-the-art double data rate (DDR); -- FlexPhase -- a circuit architecture that enables precise data transfer and simplifies system designs.
