This definition appears very rarely
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- Information technology (IT) and computers
We have 2 other definitions for QSPI
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Samples in periodicals archive:
1 MIPS at 66 MHz executing from the on-chip Flash and RAM -- 512KB embedded Flash memory -- 64 KB of static RAM accessible to core and DMA/Ethernet -- 10/100 Ethernet MAC with built-in DMA engine -- FlexCAN controller area network interface with 16 message buffers -- 8-channel 10-bit queued analog-to-digital converter (QADC) -- Four 32-bit timers with DMA capability -- Eight 16-bit timers for capture, compare, and pulse width modulation -- Three UARTs with DMA capability -- Queued serial peripheral interface (QSPI) with four peripheral chip selects -- Inter-integrated circuit (I2C) bus controller -- Four periodic interrupt timers (PITs) for alarm and countdown timing -- 17mm x 17mm x 1.
Included with the RTEK developers kit is RTEKgen, a graphical system generation program that simplifies system configuration, giving designersatures a System Integration Module with 12 programmable chip select outputs and system failure protection; four Kbytes on-chip standby RAM; queued serial peripheral interface and serial communications interface; General Purpose 16-bit Timer with nine-stage prescaler and 11 timer channels; selectable 8-bit/10-bit, eight-channel analog-to-digital converter; 46 I/O pins; 16.
Two independent UARTs, two 16-bit timers, phased-lock loop clock, software watchdog timer, general purpose input/output lines, two I2C interfaces, Queued Serial Peripheral Interface (QSPI), 4-channel direct memory access (DMA), and a glueless SDRAM controller magnify the broad appeal of this versatile new product.