What does PIT stand for?

1 MIPS at 66 MHz executing from the on-chip Flash and RAM -- 512KB embedded Flash memory -- 64 KB of static RAM accessible to core and DMA/Ethernet -- 10/100 Ethernet MAC with built-in DMA engine -- FlexCAN controller area network interface with 16 message buffers -- 8-channel 10-bit queued analog-to-digital converter (QADC) -- Four 32-bit timers with DMA capability -- Eight 16-bit timers for capture, compare, and pulse width modulation -- Three UARTs with DMA capability -- Queued serial peripheral interface (QSPI) with four peripheral chip selects -- Inter-integrated circuit (I2C) bus controller -- Four periodic interrupt timers (PITs) for alarm and countdown timing -- 17mm x 17mm x 1.

0 Host/Device/On-The-Go Controller -- Full speed/low speed transceiver -- High-speed ULPI support -- Four-channel 32-bit timers with DMA support -- Four-channel periodic interrupt timer -- 16-channel DMA controller -- 16-bit 133/266MHz DDR2/DDR controller -- Supports Mobile DDR, DDR1, and DDR2 -- Up to 135 general-purpose I/O -- System integration (PLL, SW Watchdog) -- 1.

1 MIPS at 80 MHz * Up to 128Kbytes of flash memory * 16Kbytes SRAM * Up to 56 general-purpose I/O (GPIO) * Two-channel periodic interrupt timer * Two inter-integrated circuit bus interface modules * Four-channel 32-bit timers with DMA support * Real-time clock with 32kHz crystal * 12-bit analog to digital converter (ADC) * Up to three on-chip UARTs * Available speeds: 66 MHz and 80 MHz MCF5253 embedded processor The MCF5253 is a high-performance, cost-effective embedded control solution with Hi-Speed USB OTG and an integrated USB PHY.