The pattern generator and error detector, which operate at full rate speed without external multiplexers or demultiplexers, are configured as small remotely mountable heads.
What does PG stand for?
PG stands for Pattern Generator
This definition appears very frequently and is found in the following Acronym Finder categories:
- Science, medicine, engineering, etc.
See other definitions of PG
We have 70 other meanings of PG in our Acronym Attic
- Pair Gain (telephony)
- Panzerrohr Gewinde (German: Conduit Thread; engineering supply)
- Papua New Guinea (ISO country code, top level domain)
- Parental Guidance Suggested (MPAA rating)
- Parity Game
- Parteigenosse (German: Member of NSdAP)
- Patch Guard (computer security)
- Patrol Combatant
- Patrol Combatant Ship
- Patrol Gunboat
Samples in periodicals archive:
Options include: algorithmic pattern generator, serial pattern generator, high speed Iddq monitors, ACPMU, and ASPU for testing analog functions.
This configuration allows the pattern generator to be located close to the device under test, minimizing the length of the signal cable, which helps minimize signal degradation.
Agilent's new de-emphasis signal converter allows injection of such signals when used as a front-end for Agilent's J-BERT N4903A high-performance serial BERT and the 81141/2A Serial Pulse Pattern Generator.
5 Gb/s pattern generator options are cost-efficient digital stimuli, enabling quick and accurate characterization and compliance test of high-speed serial interfaces.
The BERT-IP consists of a downloadable bitstream for the FPGA with built-in pattern generators, high speed transceiver controls and pattern receivers that enable the real time detection and display of bit errors.
The new BERTScope S Pattern Generator allows design and test engineers to generate calibrated, stressed data for jitter tolerance testing when either the device under test or a legacy BERT are used to measure bit error ratio.
a leading supplier of Design-for-Test (DFT) tools, was granted 34 claims on June 6, 2006 under United States Patent number 7,058,869 for its invention of debug, diagnosis, and yield improvement of a scan-based integrated circuit where scan chains are surrounded by pattern generators and response compactors when using a DFT (design-for-test) technology, such as Test Compression or Logic BIST (built-in self-test).