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Other topics include characterization of wavelet- based image coding systems for algorithmic fault detection, state assignment for PAL-based CPLDs, capturing processor architectures from protocol processing applications, a constraints programming approach for fabric cell synthesis, and remote path delay fault simulation.
The FastScan family supports fault models for DSM structures, including stuck-at, IDDQ, transition and path delay faults.
DFT - RT-level at-speed DFT testability analysis and automated testpoint insertion to improve small delay defect, transition delay fault (SDD-TDF) and path delay fault scan-based test coverage prior to running ATPG