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What does P2S stand for?

P2S stands for Parallel-To-Serial

This definition appears very rarely and is found in the following Acronym Finder categories:

  • Information technology (IT) and computers
  • Science, medicine, engineering, etc.

See other definitions of P2S

Other Resources:
We have 2 other meanings of P2S in our Acronym Attic

Samples in periodicals archive:

0 high-speed (480 Mbits/second) and full-speed (12 Mbits/second) * Optimized for seamless interface with the Intel Monahans Platform family * Tri-state Mode allows sharing of UTMI bus with other devices * Serial-to-parallel and parallel-to-serial conversions * 8-bit unidirectional, 8-bit bidirectional, or 16-bit bidirectional external data interface * Synchronous field and EOP detection on receive packets, and generation on transmit packets * Data and clock recovery from the USB serial stream * Bit stuffing/unstuffing, bit stuff error detection, staging register to manage data rate variations Pricing and Availability The new MoBL-USB TX2 transceiver (CY7C68000A) is available now in both 56-ball VFBGA and 56-lead QFN packages.
0 high-speed (480 Mbits/second) and full-speed (12 Mbits/second) --Serial-to-parallel and parallel-to-serial conversions --8-bit unidirectional, 8-bit bidirectional, or 16-bit bidirectional external data interface --Synchronous field and EOP detection on receive packets, and generation on transmit packets --Data and clock recovery from the USB serial stream --Bit stuffing/unstuffing, bit stuff error detection, staging register to manage data rate variations --16-bit 30-MHz, and 8-bit 60-MHz parallel interface --Supports USB 2.
0 gigahertz, single-chip design is capable of pattern generation, self-test, internal serial-to-parallel and parallel-to-serial data conversion, programmable internal clock generation (up to 2 gigabits per second pin-data rate), and data error collection.