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What does ODR stand for?

ODR stands for Octal Data Rate (high speed memory interface transfers 8 bits of data per clock cycle)


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  • Information technology (IT) and computers

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We have 71 other definitions for ODR in our Acronym Attic

Samples in periodicals archive:

To support both high speed and robust data transfer, the devices utilize advanced Rambus-specific features such as Differential Rambus Signal Level (DRSL) interface, which minimizes the signal swing and noise, and Octal Data Rate (ODR) which transfers 8 bits per clock cycle to achieve 3.
The XDR memory architecture features key enabling technologies built on patented Rambus innovations that include low-voltage, low-power Differential Rambus Signaling Level (DRSL); Octal Data Rate (ODR) technology that transfers eight bits of data each clock cycle; FlexPhase[TM] circuit technology for precise on-chip alignment of data with clock; and Dynamic-Point-to-Point (DPP) for both enhanced signal integrity and scalability.
The award-winning XDR memory architecture features key enabling technologies built on patented Rambus innovations that include low-voltage, low-power Differential Rambus Signaling Level (DRSL); Octal Data Rate (ODR) technology that transfers eight bits of data each clock cycle; FlexPhase[TM] circuit technology for precise on-chip alignment of data with clock; and Dynamic-Point-to-Point (DPP) for both enhanced signal integrity and scalability.
To support both high-speed and robust data transfer, XDR DRAM utilizes key enabling technologies built on patented Rambus innovations such as Differential Rambus Signaling Level (DRSL), which minimizes signal swing and noise; Octal Data Rate (ODR) technology which transfers eight bits of data on each clock cycle to achieve 4.
The XDR memory architecture features key enabling technologies built on patented Rambus innovations that include low-voltage, low-power Differential Rambus Signaling Level (DRSL); Octal Data Rate (ODR) technology that transfers eight bits of data on each clock cycle; FlexPhase[TM] circuit technology for precise on-chip alignment of data with clock; and Dynamic-Point-to-Point (DPP) for point-to-point signaling on the data bus.
The XDR memory architecture features key enabling technologies built on patented Rambus innovations that include low-voltage, low-power Differential Rambus Signaling Level (DRSL); Octal Data Rate (ODR) technology that transfers eight bits of data each clock cycle; FlexPhase[TM] circuit technology for precise on-chip alignment of data with clock; and Dynamic-Point-to-Point (DPP) for both enhanced signal integrity and scalability.