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Samples in periodicals archive:
Combined with the on-chip digital PLL circuitry, it complies with the Maximum Time Interval Error (MTIE) Strata 3, 4 and 4.
The CT812 also includes internal master phased lock loop (PLL) circuitry to support the Stratum 4e and Maximum Time Interval Error (MTIE) features for reliable clock synchronization across multiple boards.
KANATA, Ontario--(BUSINESS WIRE)--June 23, 1997--Mitel Semiconductor today launched the MT9042B T1/E1 PLL with Maximum Time Interval Error (MTIE) Correction.