A critical piece of intelligence integrated into the new 28nm SoC is the LSI TrueStore RC5100, a 28nm read channel featuring third-generation LSI low-density parity check (LDPC) iterative decoding architecture.
What does LDPC stand for?
LDPC stands for Low-Density Parity Check
This definition appears very rarely and is found in the following Acronym Finder categories:
- Information technology (IT) and computers
We have 6 other meanings of LDPC in our Acronym Attic
- Lung Damaging Particle
- Landing Performance Application
- Laser Diffraction Particle Analyzer
- Laser-Driven Plasma Antenna
- Left Descending Pulmonary Artery (cardiology)
- Liability for Defective Products Act
- Light Document Printing Architecture
- Lightweight Document Printing Application (Novell)
- Learning Disability Partnership Board (UK)
- Liberal Democratic Party of Belarus
- Low Density Parity Check Codes
- Liberaldemokratische Partei Deutschlands (Liberal Democratic Party of Germany; former GDR)
- Low Density Polyethylene
- Low-Density Polyethylene
- Cross-Linked, Low-Density Polyethylene (also seen as XLDPE)
- London Drug Policy Forum (UK)
- Louis Dreyfus Property Group
- Loyalist Decorative Painters Guild (Trenton, Ontario, Canada)
- Lead Director of Public Health (UK; National Health Service)
- Laser Doppler Perfusion Imaging
Samples in periodicals archive:
The RC5100 is the industry's first 28nm read channel and features a new low-density parity check (LDPC) iterative decoding architecture, which enables HDD manufacturers to achieve increased areal density, higher yield and lower power consumption for HDDs.
has announced the TrueStore[R] RC9700, a second-generation 40-nanometer (nm) read channel featuring low-density parity check (LDPC) iterative decoding technology.
Link_A_Media Devices (LAMD), a leader in the development of semiconductor SoC solutions for the data storage market, announces its low-density parity check (LDPC)-based SOC device is currently shipping in mainstream 2.
5-inch desktop drives incorporate LSI TrueStore system-on-chip (SoC) solutions, including 40nm read channels featuring second-generation low-density parity check (LDPC) iterative decoding technology.
Researchers at Rice University were amongst the first users of PICO Extreme Power and designed and evaluated a low-density parity check (LDPC) decoder for the next generation wireless handset SoC.
Low-density parity check (LDPC) iterative decoding read channel enables areal densities of 500GB per platter for 2.
In this study, Frost & Sullivan's expert analysts thoroughly examine the following technologies: forward error correction technology and related algorithmic developments, technology in implementation, turbo coding, low-density parity check codes, as well as Reed-Solomon (RS) codes.