What does IU stand for?

The architecture contains six independent execution units, including two integer units, two floating- point units (FPUs), a non-blocking load/store unit and a branch unit.

Each of the Power3-based cores on the Power4 microSMP will have three integer units, and the combined six units should be able to process ten instructions per clock cycle (if not more).

MPC5123 product features * e300 core * Built on Power Architecture technology * 32KB instruction cache and 32KB data cache * Double-precision floating point unit and dual integer units * Up to 400 MHz performance, delivering 800 MIPS * User-programmable 32-bit RISC multimedia core operating at up to 200 MHz * Integrated display controller supporting up to 720p (1280x720) and WXGA (1366x768) resolution * 12 programmable serial controllers supporting UART, SPI, AC97, I2S * SDRAM DDR-I/DDR-II/mobileDDR memory controller * 10/100 Fast Ethernet media access controller (MAC) * Three I2Cs * PCI 2.

The CPU has 32-bit integer unit and 64-bit double precision floating point unit that meet the IEEE754 standard.

These individual microprocessors will include two floating point units, plus three integer units and an assortment of load and branch units.

Our C/C++ compiler, together with the MULTI IDE, makes it easy to design efficient code that keeps the MPC7450's integer units, floating point unit, and vector processing units operating at full tilt without having to program in assembly language.

The features implemented by Toshiba to handle the rigors of space and ensure reliable operation include: -- MIPS instruction set -- 36-bit address bus (64-bit virtual address), 64-bit data bus -- 8KB instruction cache, 8KB data cache with 8-bit error detection & correction -- 25MHz pipeline frequency -- 50MHz external clock (a selectable feature for the bus clock rate) -- 64-bit general-purpose registers, integer unit, floating point registers, and floating point unit -- Operating voltage of 3.

The Triple Issue Integer unit includes a 6-stage pipeline with bi-directional data pre-fetching and no data misalignment penalty.