What does ILP stand for?

Instruction-Level Parallelism

This definition appears very rarely

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Samples in periodicals archive:

The architecture exploits multiple levels of parallelism: * task-level parallelism between the system processor, DSP processor and DPU * data-level parallelism (DLP) with multiple lanes executing the same instructions on different data in parallel * instruction-level parallelism (ILP) via very long instruction word (VLIW) driving multiple arithmetic logic units (ALUs) per lane * sub-word single instruction multiple data (SIMD) in which each ALU can operate on multiple operands On the DPU, a kernel function runs identically on every lane processing different data.

Stream Processors, Inc. Announces Breakthrough Digital Signal ...

35mW/MHz by efficiently supporting instruction-level parallelism and data-level parallelism.

IMEC's Software-Defined Radio Concept Compliant with 3GPP-LTE

This enables Secure64 to capitalize on the chip's large register sets and high instruction-level parallelism to significantly boost network performance.

Top-Flight Team Launches Secure64 With Core Patent Technology to Make ...