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Samples in periodicals archive:
The researchers explore grouping proofs, the feasibility of elliptic curve cryptography on wireless identification and sensing platforms (WISP), minimal instruction set computer (MISC) processor design, patient compliance monitoring for home telecare, and different approaches to tracking the supply chain of consumer food products.
Transcede devices include the Cortex A9 multi-core symmetric multiprocessing (SMP) reduced instruction set computer (RISC) processors from ARM, combined with digital signal processors (DSPs) from CEVA.
TAEC) has unveiled a new 32-bit single-chip MIPS-based reduced instruction set computer (RISC) microcontroller (MCU) family.
TI will showcase how designers can boost product value by taking advantage of the MSP430's ultra-low-power architecture; integrated high-performance analog and digital peripherals; and modern, 16-bit reduced instruction set computer (RISC) CPU.
Toshiba will maintain continuity between the development tools for the complex instruction set computer (CISC) microprocessor TLCS-900 series and the TX19, providing a seamless language tool environment.
The RX CPU implements a complex instruction set computer (CISC) architecture that integrates and significantly extends the capabilities of Renesas' existing 16-bit and 32-bit MCU products, while providing compatibility that protects customer designs that use existing Renesas MCUs.
Zebra Technologies , a global leader in delivering printing solutions for business improvement, today unveiled the LP and TLP 2844-Z printers, Zebra's newest 4-inch direct thermal and thermal transfer desktop printing solutions with Zebra programming language (ZPL) capability and a 32-bit reduced instruction set computer (RISC) micro processor for superior performance and exceptional horsepower.
3V I/O, the Toshiba TX49/H2 microprocessor reduced instruction set computer (RISC) core is an optimized five stage pipeline with a 64-bit data path, based on MIPS architecture.