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Samples in periodicals archive:
Companies spend typically 10x their algorithm development time ensuring the algorithmic model, system-level model, RTL model and gate level models all represent the same design and we have seen many examples where costly re-spins were required when errors were not found up front.
These previous attempts, as well as other commercial offerings available today, were unable to provide the design partitioning, synchronization, convergence, and single viewing environment between testbenches, behavioral models, gate level models, transistor level netlists, and parasitic back annotation required by mixed-signal design engineers.
RTL or gate level models provide the highest accuracy, in addition to eliminating the writing of redundant system level models.