What does EBI stand for?

With a processor clock running at 400 MHz, twin parallel External Bus Interfaces (EBI) supporting Dual Data Rate DRAM (DDR2) at 133 MHz and integrating High Speed (480 Mbps) EHCI-compliant USB Host and Device Ports with on-chip transceivers, Ethernet MAC, as well as two interfaces for MMC 4.

The external bus interface (EBI) is clocked at 133 MHz for high-speed transfers to off-chip memories.

The ARM926EJ-S System CoreWare IP consists of proven CoreWare IP functions such as the ARM926EJ-S core, Ethernet Controller, Vectored Interrupt Controller, UARTs, GPIOs, IIC, and an external bus interface unit.

0 with on-the-go capability and a SRAM/SDRAM external bus interface.

Dedicated flash can be connected via the external bus interface (EBI) or SPI.

9 GFLOPS (at 266MHz operation) ---------------------------------------------------------------------- CPU core SH-4A 32-bit RISC ---------------------------------------------------------------------- On-chip RAM 16 Kbytes ---------------------------------------------------------------------- Cache memory Instructions: 32Kbytes; Data: 32Kbytes (4-way set associative) ---------------------------------------------------------------------- External memory/ external bus interfaces -- DDR-SDRAM memory controller - DDR-SDRAM connectable with 32-bit bus width - Maximum operating frequency: 133MHz -- Local bus state controller (BSC) - SRAM, burst ROM, etc.

This impressive boost in performance arises from the addition of a hardware floating point unit, increased frequency, and an enhanced external bus interface.

0 Full Speed Device -- Clock and Power Management -- Low Power Modes -- Active, Standby, Sleep, Stop1, Stop2 -- Color LCD Controller supports STN, TFT, AD-TFT -- Ten Input, 10-bit A/D Converter with Integrated Touch Screen Controller -- Four DMA Channels -- SDRAM Controller -- NAND Flash Boot Support -- Serial Interfaces -- Three 16C550-type UARTs, 9-bit capability, and Classic IrDA (115 kbit/s) -- SSP -- I2C -- SSP to I2S Codec Converter -- External Bus Interface -- Six Chip selects Providing Glueless Interface to Off-Chip -- Memories and Peripherals -- 24 Address Bits -- Data Bits -- 32 Data Bits (LH79524) -- 16 Data Bits (LH79525) -- Real Time Clock (RTC) -- Operates from 32.