What does DLL stand for?

Digital Delay Locked Loop

This definition appears very rarely and is found in the following Acronym Finder categories:

Information technology (IT) and computers

Other Resources:

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Delaney Lund Knox Warren & Partners Dan Lain-Lainnya, (Indonesian: And So Forth; Et cetera) Data Link Layer Data Link Level Data Link Library (aviation) David Lloyd Leisure (various locations) Delay Lock Loop (FPGA) Design Limit Load (aviation) Dial Long Line Equipment Dial Long Lines		Direction du Livre et de la Lecture (French: Directorate of Books and Reading) Disapproved Lower Level Discharge Line Length Disclosure Limitations List Double-Loop Learning Doubly Linked List Down Line Loading Dynamic Link Library Dynamically Loaded Library Double Leading Logarithmic Approximation

Samples in periodicals archive:

In addition to expansive on-chip memory resources, the Virtex-E FPGAs feature eight digital delay locked loops (DLLs) for on- and off-chip clock management and programmable support for multiple differential signaling standards, including LVPECL, LVDS and Bus LVDS.

Xilinx Ships World's Highest Density FPGA; Virtex-E Delivers ...

The Virtex-II architecture helps designers solve these challenges with enhanced global clock distribution and multiple digital delay locked loops (DLLs) running at over 400 MHz.

Xilinx Unveils New FPGA Architecture to Enable High-performance, Ten ...

2 million gates; 832 Kbits of True Dual-Port(TM) internal block RAM; eight digital delay locked loops (DLLs) capable of over 300 MHz clock frequency for system timing; and 20 I/O standards including LVDS, BusLVDS and LVPECL.

Xilinx Announces Industry's First Internet Resource for Comprehensive ...