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Samples in periodicals archive:
Integrating CMOS and high voltage devices on SOI substrates with deep trench isolation (DTI) offers minimum isolation and device area, minimum substrate leakage, improved radiation hardness and high-temperature operation.
In developing its I3T50 technology, AMIS employed a proprietary deep trench isolation (DTI) technique that allows isolation distances between an ASIC's high-voltage devices to be dramatically reduced.
3 volt CMOS, deep trench isolation, lateral PNP transistors, MIM and MIS capacitors, high-performance varactors, poly and Nwell resistors, and high-Q inductors.
35-micron platform that also includes CMOS, deep trench isolation, lateral PNP transistors, MIM and MIS capacitors, high-performance varactors, poly and N-well resistors, and high-Q inductors.
To overcome traditional trade-offs between high- speed and high-voltage operation and achieve excellent ratings in both these areas, the process employs advanced fabrication techniques, including state-of- the-art epitaxy, high-energy implantation, deep trench isolation, and rapid thermal processing.
Both processes feature very high-density MIM capacitors of 4 fF/micron(2) and deep trench isolation to enable noise isolation in noise-sensitive products, such as TV tuners.
We apply our design expertise to fully exploit SiGe's deep trench isolation process, maximizing the attendant benefits of noise-reduction and circuit isolation, and yielding very high-density, high-performance RF designs.
Deep trench isolation is also offered as a process option for enhanced RF performance and noise isolation.