Low-jitter 2x to 32x phase locked loop eliminates the need for an external, low-jitter clock multiplier to match the interpolated rate.
What does CLKMUL stand for?
CLKMUL stands for Clock Multiplier
This definition appears somewhat frequently and is found in the following Acronym Finder categories:
- Information technology (IT) and computers
- Chep Lap Kok (Hong Kong airport)
- Contact Lens King (optometry)
- Corel RAVE (file extension)
- Coupe Leicht Kurtz (Mercedes Benz model)
- Current Level of Knowledge
- Clock 16 Generator (unit)
- Clock Estimate (Bluetooth)
- Community Living Kawartha Lakes (Canada)
- Clock Native (Bluetooth)
- Computer-Controlled Continuously Variable Lockup (automobile transmissions)
- Capacitively-Loaded Loop
- Celestial Labs Ltd. (India)
- Center for Learning and Leadership (various organizations)
- Chief of Legislative Liaison
- Child Life-Line (est. 1994)
- Chronic Lymphatic Leukemia Foundation
- Chronic Lymphocytic Leukemia
Samples in periodicals archive:
AMCC 10G XAUI to XFI transceiver Avago SFPs for client interfaces Broadcom 10G SFI-4 to XFI transceiver Gennum adaptive cable equalizer, cable driver, SDI reclocker Motorola PowerQuiccII(TM) microprocessor NDK 3rd overtone crystals Powerone DC-DC POL converters Silicon Labs Any-Rate Clock Multipliers and Jitter Attenuators Suntsu LVCMOS oscillators Vitesse 10G XAUI to XFI transceiver Xilinx Vitex(R)-5 FPGAs Zarlink system synchronizer, clock generation "We've been fortunate to have the ongoing support of these companies over several generations of our reference platforms.
Pericom Semiconductor Corporation (NASDAQ:PSEM) has expanded its SiliconClock IC portfolio with three new PLL clock multipliers targeting consumer electronics such as Set-top Box/DVR/PVR and HDTV, as well as Telecommunication Line Cards including T1/E1/OCxx.
The SMI5026 is a 16:2 Multiplexer with on-chip Clock Multiplier Unit (CMU) and integrated DQPSK Precoder.
8 /PRNewswire/ -- Texas Instruments (TI) today announced a programmable clock multiplier with low jitter of 60 psec and in- system spread spectrum adjustment that improves performance, simplifies development and saves cost in consumer applications.
Each DSPLL clock multiplier can be configured to generate any frequency from 2 kHz to 808 MHz from a 2 kHz to 710 MHz input.
20 /PRNewswire/ -- Texas Instruments (TI) today announced a clock multiplier that integrates three on-chip phase locked loop (PLL) components to provide industry-leading flexibility and performance, including cutting period jitter by up to 70 percent compared to existing solutions and minimizing electromagnetic interference (EMI).
The AD9146 D/A converter also integrates an 8-bit LVDS (low-voltage differential signaling) interface and low-noise PLL (phase-locked loop) clock multiplier, which allow design engineers to implement up to six transmit channels using half the PCB space previously required.