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Samples in periodicals archive:
ZenTime-GT employs multiple timing optimization techniques including: buffer insertion, such as buffer tree construction and restructuring; gate sizing for discrete drive strengths; pin permutation; use of inverted logic gates; and output stage sizing.
After exhausting all means of timing improvements through IPO sizing, buffer insertion, routing modifications, etc.
When producing final detailed placement, Sonar employs its built-in physical synthesis engine that includes logic re-structuring, technology mapping, cell sizing, buffer insertion, and post-placement optimization.