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What does ATPG stand for?

Automatic Test Pattern Generation


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Association Tunisienne du Planning Familial (French: Tunisian Association of Family Planning; est. 1968)
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American Tax Policy Institute (Washington, DC)
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Samples in periodicals archive:
Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Arrow Electronics successfully deployed Synopsys' TetraMAXA; automatic test pattern generation (ATPG) with multicore processing to significantly reduce the time needed to generate high-quality manufacturing tests.
Several of the papers explore memory testing, automatic test pattern generation, single-event upsets, diagnosis, reconfigurable systems, and sigma- delta modulators.
As part of this strategy, Mentor is uniting its award-winning embedded compression and automatic test pattern generation (ATPG) technology with the leading built-in self-test (BIST) technology from recently acquired LogicVision into a new product line, called Tessent[TM].
The path report generated by Refocus is provided as input to Mentor Graphics' automatic test pattern generation (ATPG) products, FastScan[TM] or TestKompress[R].
The specifications target requirements for logic synthesis, physical synthesis, library modeling, power analysis, special cells, design-for-test (DFT) and automatic test pattern generation (ATPG).
About Mentor Graphics Design-for-Test Tools Mentor Graphics provides the industry's broadest portfolio of DFT solutions for today's System-on-Chip and deep submicron designs, including integrated solutions for scan, automatic test pattern generation (ATPG), electronic design and test (EDT), advanced memory test, boundary scan, logic built-in self-test and a variety of DFT-related flows.
The TestKompress tool fits easily into most scan-based design flows and offers the same at-speed test capabilities as Mentor Graphics FastScan(TM), the industry-leading automatic test pattern generation (ATPG) tool.
The development partnership between Mentor and STARC seeks to fulfill proposed delay defect detection requirements from STARC and its client companies by incorporating new technologies into Mentor's Automatic Test Pattern Generation (ATPG) IC test tools that will ensure the highest quality for tested chips.

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